Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

wccftech.com

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

wccftech.com

Arthur Besse@lemmy.ml to

RISC-V@lemmy.mlEnglish · 6 天前

Alibaba's XuanTie C950 chip hits 30 tokens/second, with a 1.9-second first-token latency, on Qwen-3.8 27B - no emulation layer required.

cross-posted from: https://hexbear.net/post/9331536

Looks like China wants the whole chain to be open source with the RISC-V push, Alibaba’s motivation for it was partly party directive/laws and also RISC-V has no licensing pricing so they can sell this much cheaper.

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