Rekall Incorporated@piefed.socialEnglish · 3 days agoArm stock declines massively as Qualcomm acquires RISC-V designer Ventanaplus-squarewww.techradar.comexternal-linkmessage-square2linkfedilinkarrow-up117arrow-down10cross-posted to: riscv@programming.dev
arrow-up117arrow-down1external-linkArm stock declines massively as Qualcomm acquires RISC-V designer Ventanaplus-squarewww.techradar.comRekall Incorporated@piefed.socialEnglish · 3 days agomessage-square2linkfedilinkcross-posted to: riscv@programming.dev
cm0002@infosec.pub · 2 days agoQEMU 10.2 Expands RISC-V, PowerPC, and s390x Emulation Capabilitiesplus-squarelinuxiac.comexternal-linkmessage-square0linkfedilinkarrow-up15arrow-down10
arrow-up15arrow-down1external-linkQEMU 10.2 Expands RISC-V, PowerPC, and s390x Emulation Capabilitiesplus-squarelinuxiac.comcm0002@infosec.pub · 2 days agomessage-square0linkfedilink
cm0002@mander.xyz · 2 days agoParrot 7.0 Ethical Hacking Distro Released with KDE Plasma, RISC-V Supportplus-square9to5linux.comexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down11
arrow-up11arrow-down1external-linkParrot 7.0 Ethical Hacking Distro Released with KDE Plasma, RISC-V Supportplus-square9to5linux.comcm0002@mander.xyz · 2 days agomessage-square0linkfedilink
Rekall Incorporated@piefed.socialEnglish · 7 days agoIndia unveils a homegrown dual-core 1GHz RISC-V processorplus-squarewww.theregister.comexternal-linkmessage-square3linkfedilinkarrow-up121arrow-down10
arrow-up121arrow-down1external-linkIndia unveils a homegrown dual-core 1GHz RISC-V processorplus-squarewww.theregister.comRekall Incorporated@piefed.socialEnglish · 7 days agomessage-square3linkfedilink
cm0002@lemy.lol · 7 days agoNewer RISC-V CPUs Vulnerable To Spectre V1 - Linux Mitigation Patches Postedplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up13arrow-down10
arrow-up13arrow-down1external-linkNewer RISC-V CPUs Vulnerable To Spectre V1 - Linux Mitigation Patches Postedplus-squarewww.phoronix.comcm0002@lemy.lol · 7 days agomessage-square0linkfedilink
cm0002@literature.cafe · 10 days agoRISC-V-based ESP32-P4 handheld integrates AMOLED display and LoRaplus-squarelinuxgizmos.comexternal-linkmessage-square0linkfedilinkarrow-up116arrow-down10
arrow-up116arrow-down1external-linkRISC-V-based ESP32-P4 handheld integrates AMOLED display and LoRaplus-squarelinuxgizmos.comcm0002@literature.cafe · 10 days agomessage-square0linkfedilink
cm0002@toast.ooo · 16 days agoLinux 6.19 For RISC-V Brings Parallel CPU Hotplugging, Zalasr Ratified ISA Supportplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up15arrow-down11
arrow-up14arrow-down1external-linkLinux 6.19 For RISC-V Brings Parallel CPU Hotplugging, Zalasr Ratified ISA Supportplus-squarewww.phoronix.comcm0002@toast.ooo · 16 days agomessage-square0linkfedilink
cm0002@literature.cafe · 18 days agoTenstorrent Blackhole Support & Other New RISC-V + ARM64 Hardware In Linux 6.19plus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up15arrow-down10
arrow-up15arrow-down1external-linkTenstorrent Blackhole Support & Other New RISC-V + ARM64 Hardware In Linux 6.19plus-squarewww.phoronix.comcm0002@literature.cafe · 18 days agomessage-square0linkfedilink
cm0002@infosec.pub · 1 month agoRISC-V Testing Lapse Resulted In Wrong MIPS RISC-V Vendor ID Landing In Linux 6.18plus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up13arrow-down10
arrow-up13arrow-down1external-linkRISC-V Testing Lapse Resulted In Wrong MIPS RISC-V Vendor ID Landing In Linux 6.18plus-squarewww.phoronix.comcm0002@infosec.pub · 1 month agomessage-square0linkfedilink
cm0002@infosec.pub · 1 month agoArduino Nesso N1 Debuts as a Compact RISC-V IoT Controller with Wi-Fi 6, Thread, and LoRa Connectivityplus-squarelinuxgizmos.comexternal-linkmessage-square0linkfedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkArduino Nesso N1 Debuts as a Compact RISC-V IoT Controller with Wi-Fi 6, Thread, and LoRa Connectivityplus-squarelinuxgizmos.comcm0002@infosec.pub · 1 month agomessage-square0linkfedilink
cm0002@no.lastname.nz · 1 month agoCanonical Gets Flutter Up And Running On RISC-V For Ubuntuplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up19arrow-down11
arrow-up18arrow-down1external-linkCanonical Gets Flutter Up And Running On RISC-V For Ubuntuplus-squarewww.phoronix.comcm0002@no.lastname.nz · 1 month agomessage-square0linkfedilink
cm0002@no.lastname.nz · 1 month agoMainline Linux Patches For The VisionFive 2 Lite: RISC-V For As Little As $19.9 USDplus-squarewww.phoronix.comexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down10
arrow-up12arrow-down1external-linkMainline Linux Patches For The VisionFive 2 Lite: RISC-V For As Little As $19.9 USDplus-squarewww.phoronix.comcm0002@no.lastname.nz · 1 month agomessage-square0linkfedilink
cm0002@lemmings.world · 2 months agoRISC-V takes first step toward international standardization as ISO/IEC JTC1 grants PAS Submitter statusplus-squareriscv.orgexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down10
arrow-up12arrow-down1external-linkRISC-V takes first step toward international standardization as ISO/IEC JTC1 grants PAS Submitter statusplus-squareriscv.orgcm0002@lemmings.world · 2 months agomessage-square0linkfedilink
cm0002@lemmings.world · 2 months agoEasy RISC-Vplus-squaredramforever.github.ioexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down10
arrow-up12arrow-down1external-linkEasy RISC-Vplus-squaredramforever.github.iocm0002@lemmings.world · 2 months agomessage-square0linkfedilink
cm0002@lemmy.zip · 2 months agoBolt Graphics unveils Zeus GPU built on RISC-V and path tracing techplus-squarewww.theregister.comexternal-linkmessage-square0linkfedilinkarrow-up17arrow-down10cross-posted to: riscv@programming.dev
arrow-up17arrow-down1external-linkBolt Graphics unveils Zeus GPU built on RISC-V and path tracing techplus-squarewww.theregister.comcm0002@lemmy.zip · 2 months agomessage-square0linkfedilinkcross-posted to: riscv@programming.dev
Scoopta@programming.dev · 2 months agoRISC-V CPUs with H extension?plus-squaremessage-squaremessage-square1linkfedilinkarrow-up15arrow-down10
arrow-up15arrow-down1message-squareRISC-V CPUs with H extension?plus-squareScoopta@programming.dev · 2 months agomessage-square1linkfedilink
cm0002@lemmings.world · 2 months agoRISC-V SBI and the full boot processplus-squarepopovicu.comexternal-linkmessage-square0linkfedilinkarrow-up12arrow-down10
arrow-up12arrow-down1external-linkRISC-V SBI and the full boot processplus-squarepopovicu.comcm0002@lemmings.world · 2 months agomessage-square0linkfedilink
cm0002@lemmy.zip · 2 months agoUpbeat and SiFive Launch Ultra-Low Power RISC-V MCU with AI Accelerationplus-squarelinuxgizmos.comexternal-linkmessage-square0linkfedilinkarrow-up19arrow-down10
arrow-up19arrow-down1external-linkUpbeat and SiFive Launch Ultra-Low Power RISC-V MCU with AI Accelerationplus-squarelinuxgizmos.comcm0002@lemmy.zip · 2 months agomessage-square0linkfedilink
