And beyomd PCIe 4 the electrical interconnect requirements become significantly more challenging due to the faster switching rates, so even the PCBs have to be reworked.

You’d just be losing out on the interlink bandwidth improvements (I.e large reads, maybe write performance too), you’d still be getting the generational improvement in flash storage speed and the controller which would carry over to previous generations of PCIe links where the throughput was not previously limited by PCIe bandwidth