• @Buffalox@lemmy.world
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    8 hours ago

    It means pointer width.

    https://en.wikipedia.org/wiki/64-bit_computing

    64-bit integers, memory addresses, or other data units[a] are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size.

    It also states Address bus, but as I mentioned before, that doesn’t exist. So it boils down to instruction set as a whole requiring 64 bit processor registers and Databus.
    Obviously 64 bits means registers are 64 bit, the addresses are therefore also 64 bit, otherwise it would require type casting every time you need to make calculations on them. But it’s the ability to handle 64 bit registers in general that counts, not the address registers. which is merely a byproduct.

    • @barsoap@lemm.ee
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      07 hours ago
      1. The whole article overall lacks sources.
      2. That section is completely unsourced.
      3. It doesn’t say what you think it says.

      You were arguing the definition of “X-bit CPU”. We’re not talking about “X-bit ALU”. It’s also not up to contention that “A 64-bit integer is 64 bit wide”. So, to the statement:

      Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, address buses, or data buses of that size.

      This does not say which of “processor register, address buses, or data buses” applies to CPU and which to ALU.

      Obviously 64 bits means registers are 64 bit, the addresses are therefore also 64 bit,

      Having 64 bit registers doesn’t necessitate that you have 64 bit addresses. It’s common, incredibly common, for the integer registers to match the pointer width but there’s no hard requirement in theory or practice. It’s about as arbitrary a rule as “Instruction length must be wider than the register size”, so that immediate constants fit into the instruction stream, makes sense doesn’t it… and then along come RISC architectures and split load immediate instructions into two.

      otherwise it would require type casting every time you need to make calculations on them

      Processors don’t typecast. Please stop talking.